There are known processors which comprise one or more functional blocks in addition to a core. Such functional blocks may include, for example, a bus controller, an input/output interface, a direct memory access (DMA), a timer, etc. Furthermore, the processor core may include various functional components for instruction fetch, instruction decode, the management of processor registers, etc. In addition, the core may comprise one or more arithmetic logic units, multiplication units, divider units, floating point units, interrupt controllers, etc.
In program codes applied in conventional processors, one instruction word refers to the operation of one or more functional blocks, such as data retrieval from a memory toga register, starting of a timer, addition of two numbers, etc. Typically, the length of such instruction words is in the order of one to four bytes. Also, processors have been developed to apply very long instruction words, (VLIW), whose length may be several bytes. Thus, such a very long instruction word can be used for the transmission of an instruction even for each functional unit of the processor. The instruction word is thus divided into elements, in which each element contains an instruction for a given functional block. By means of such an arrangement, it is possible to accelerate the processing of program codes to some extent, because the number of steps to retrieve the instructions is reduced. The decoding of very long instructions can also be divided into parts, wherein each functional unit is provided with a separate decoder to perform the decoding of the instructions for this functional unit. Several decoders can thus decode parts of an instruction word substantially simultaneously.
The performance of processors has been continuously increasing. For example, the clock frequencies of processors have multiplied within a few recent years. However, the increase in the performance also causes problems, because the power consumption rises in proportion to the increase in the clock frequency. On the other hand, the power consumption can be reduced to some extent by reducing the operating voltage, as the power consumption is proportional to the square of the change in the operating voltage. Nevertheless, the operating voltage cannot be limitlessly reduced without affecting the reliability of operation and, on the other hand, the increase in the clock frequency sets its own limits to the reduction of the operating voltage.
Particularly, the increase in the power consumption causes problems in portable devices, in which the operating voltage is provided by batteries. The capacity of the batteries is limited, wherein it would be advantageous to adjust the power consumption according to the need of use. On the other hand, increased power consumption will also lead to increased warming-up, which causes problems in the arrangement of cooling and may also shorten the lifetime of the processor.
In some processors, the power control is implemented by monitoring the temperature and power consumption of the processor, wherein the operating voltage and/or the clock frequency are adjusted when necessary. Another solution applied for controlling the power consumption is based on setting some of the functional blocks of the processor in a power saving mode or turning them completely off at the stage when no operations are being processed in the functional block. Such techniques are based on the use of specific instruction words or flags. Thus, the program code is provided with either a program command to set the mode of a functional block as desired, or the instruction word is used to set a specific flag (bit or bit sequence) whose state will determine the mode of a given functional block. However, such methods have e.g. the problem that the decoding of the instruction words (e.g. Huffman decoding) must be performed normally also for those functional blocks which have been set in a power saving mode. The decoding of instruction words is very power-consuming, wherein such a solution is not advantageous for use in processors applying the architecture of very long instruction words. Furthermore, such a method cannot be used in such processor architectures in which the number of instructions in one instruction word is different from the number of functional units in the processor. It is obvious that said Huffman decoding is only an example of a decoding method but also other decoding methods are known which can be used in connection with processors.
In processors of prior art, the internal modes of functional blocks in the core cannot be set block by block but as a unit. Thus, if the core is set in a power-saving mode, the functional blocks of the core cannot be used, wherein e.g. the decoding of instructions will be stopped. Correspondingly, if the core is in the normal mode, also all the functional blocks of the core will be in the normal mode and will consume power, irrespective of whether they are used or not.
FIG. 1 shows, as a functional diagram, a decoding arrangement for instruction words used in a prior art processor e.g. for power saving. Each instruction word is provided with one or more flags which are used to control the power saving of the functional blocks in the processor. The instruction word prefetch block, fetches 101 the instruction word 102 to be performed next and transfers one or more flags 103 for controlling e.g. power saving to a decoder for their interpretation. The decoder transfers 104 the interpretation data to control registers, of which each sets 105, in a corresponding manner, the mode of a given functional block to a power saving mode or to the normal mode according to the value of the flag in the instruction word. In the processor according to this arrangement, instruction words must be decoded all the time so that the power saving flags can be interpreted.